1. Field of the Invention
The invention relates to semiconductor devices having transistors operating with high and low voltages.
2. Description of Related Art
In conventional semiconductor devices having both high-voltage transistors (operation voltage of about 1.8-5.0 V with a thicker gate oxide) and low-voltage transistors (operation voltage of about 1.0-2.5 V with a thinner gate oxide) such as MOS transistors, a design goal has been to manufacture a device in which size is minimized and the number of heat processes used in manufacturing are limited, in order to avoid a short channel effect. However, although the reduced heat processes were good for the manufacture of low-voltage transistors, the reducing of heat processes led to the creation on the device of a high-voltage transistor that was less reliable for high-voltage operations. However, if the number heat processes were increased, then this would have a disadvantageous effect on the low-voltage transistor, causing diffusion effects in the low-voltage transistor that reduces its performance.
Thus, designers adopted light-doped drain (LDD) technologies, which added one or more additional drain layers or regions to the transistors, in an effort to reduce the electric field density in the vicinity of the drain. However, the effects of LDD implantation or LDD doping varied depending on whether or not the eventual transistor was to be a high-voltage or low-voltage transistor on the semiconductor device. For low-voltage transistors, characteristics such as higher impurity density and shallower junction depth were preferred. In contrast, high-voltage transistors require a low impurity density but deeper junction depth characteristics.
This created a tradeoff. Varying LDD regions created reliability degradation problems in both high and low-voltage transistors. Overcoming the reliability problems for the high-voltage transistors resulted in a need to diffuse, which required an increase in thermal processing, or an increase in the energy of ion implantations. However, this increase in ion implantation energy led to increases in junction depth of the LDD region in low-voltage transistors, which limited the transistor's performance due to poor short channel immunity.
In particular, and as will be described more fully below, the conventional method of manufacturing a semiconductor device was one direct reason for the above-noted problems. FIG. 1 illustrates a general method of forming a conventional semiconductor device. In particular, in Step S0.1 a thick gate oxide is formed for a high-voltage transistor by means of thermal oxidization. In Step S0.2 the thick gate oxide is removed at low-voltage transistor region. Then a thin gate oxide is formed there for low-voltage transistor region by thermal oxidization. In Step S1 the gate electrodes, and islands of the eventual NMOS and PMOS transistors are formed on a Si substrate. Thereafter in Step S2, oxidation processes or thermal processes are conducted in order to build-up oxide films to protect the Si substrate and the gate electrodes, in preparation for further doping processes to form the eventual high or low-voltage NMOS or PMOS transistors of a semiconductor device. After the formation of the gate electrode in Step S1 and the oxidation/thermal processes of Step S2 are completed, then the process of doping or ion implantation to form either the high or low-voltage transistor region is performed, where the islands (having been formed ahead of time) are doped or implanted with the LDD regions, n-type and p-type regions, and source/drain regions (Steps S3 and S4).
The problem with this conventional method is that the regions where the high-voltage transistors were to be formed could not diffuse LDD sufficiently, because the oxidation processes (Step S2) took place before the LDD doping processes in steps S3. Particularly, the junction depth of the high-voltage transistor was not sufficiently deep. Therefore, the LDD junction depths for both the high-voltage and low-voltage transistors were about equal, and the high-voltage transistor was subject to degraded reliability. Hence, overall device performance was reduced.
One effort to overcome this problem is described in Laid-Open Japanese Patent Publication No. 2000-31292. This patent describes a technology whereby the reliability of the high-voltage transistor is secured without degrading the characteristics of the low-voltage transistor by changing the structure of the LDD regions of the high-voltage transistor and the low-voltage transistor. In JP 2000-31292, the LDD structures of the low-voltage transistor and the high-voltage transistor are changed simply by changing the implantation conditions only.
However, in the most recent LSI processes, in which the thermal hysteresis is sufficiently low from the LDD implantation process performed after the oxidation process, it is difficult to form a smooth junction at the LDD end, and consequently it is difficult to ensure the reliability of the high-voltage transistor. Accordingly, LSI processes desire a method of forming a semiconductor device having high and low-voltage transistors that ensures the acceptable reliability and performance of the high-voltage transistor.